A Technique for Mapping Optimization Solutions into Hardware

Feedback neural architectures have addressed a myriad of optimization problems—almost exclusively in slow software simulation. Speed is promised only when implemented in high-speed recurrent hardware. Unfortunately, hardware’s discrepancies from ideal conspire to produce poor solutions. This paper describes a recurrent hardware-in-the-loop learning procedure that maps idealized solutions of optimization tasks into non-ideal recurrent hardware. The technique is demonstrated on a general purpose analog VLSI chip with winner-takes-all and resource allocation problems. For all problem sizes that fit into the chip the network finds very good solutions with high probability. Theoretical analysis and empirical measurements indicate that the noise limits the hardware to 30 neurons, but this increases dramatically with reduced noise.